0. Acknowledgments 8. Performance 6.2. Performance Evaluation

We have demonstrated that a self-timed on-chip cache can be produced and readily interfaced to an asynchronous microprocessor. In some parts of the design the asynchro-nous style provides a distinct advantage over a conventional , synchronous approach. An example of this is the mechanism used to reduce power consumption by switching off the RAM sense amplifiers when they are known to have produced their output; this method has also been applied to ostensibly synchronous circuits in the past. The self-timing, typically performed by using carefully matched timing signals within the full custom logic can create problems however. A good example of this is in the CAM where two serial self-timed paths must be used. This is an unfortunate source of excess power consumption as the " bundle " timed by the second of these signals comprises a single wire. The exploitation of sequential cache accesses is a valuable mechanism for reducing power consumption. Avoiding the precharge not only saves significant power but also reduces the access time needed for subsequent cycles. This can be exploited in an asynchronous environment because even small differences in speed may be taken advantage of. This may be contrasted with a synchronous system where a speed difference must exceed a whole clock cycle before it becomes useful. The cache therefore provides a good example of a system which provides " average case performance " , an often used argument in favour of asynchronous systems. This is not just a consequence of a data dependent cycle time; it is also necessary that the environment provides suitable operating conditions. In this case cycles of different lengths are closely interleaved, there is an elastic buffer (the proces-sor's instruction prefetch buffer) downstream and the address interface is sufficiently fast to provide a ready stream of addresses. The cache line fill mechanism provides a great deal of flexibility in a simple manner. Despite servicing the micro-processor's requests and operating the memory interface as autonomous asynchronous processes, it allows the cache to be completely non-blocking. It is also completely deter-ministic and arbiter-free. Although the benefits may be less marked there is no reason why an analogous mechanism could not be employed in a synchronous system. The work described in this paper was carried out as part of ESPRIT project 6909, OMI/DE-ARM (the Open Microprocessor systems Initiative-Deeply Embedded ARM Applications project). The authors are grateful for this support from the CEC. The …